Packaging

Integrated circuits are typically enclosed in packages that allow insertion into printed wiring boards and all types of circuit enclosures.  The package provides environmental isolation and also electrical connection from pins on the package exterior to the interconnect on the chip itself.  Packages are ideally designed to have no impact on the performance of the chip, but all packages introduce some level of signal cross-talk and other undesirable effects that must be understood and minimized.

To model packages in Analyst, the geometry is specified either by creating a three-dimensional model within the embedded CAD tool, or by importing geometry from another CAD package.  For packages that contain a multiple layer interconnect, the individual layers can also be defined using GDS-2 or DXF specification that can be exported from a layout tool.  Standard package media are pre-defined in the Analyst materials library, and new custom material specifications can easily be made if necessary during model construction.

Packages typically have many bonding pads or other signal trace terminations that each represent a microwave “port”.  Signal traces that exit the package on a common plane can be treated collectively as a multiple-conductor transmission line (with separate modes corresponding to excitation of each trace), or individually as isolated ports.  Ports may be de-embedded and also re-normalized to a specified impedance.  If the package potentially radiates microwave energy, the entire structure can be modeled within an air volume with “open” boundary conditions on the exterior model surfaces. 

Using parallel processing, typical packaging problems involving complex geometry and a large number of ports can be modeled very efficiently by domain and/or spectrum decomposition that is done automatically by the Analyst solvers.